Memory devices are conventionally provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory devices including random-access memory (RAM), read-only memory (ROM), synchronous dynamic random-access memory (SDRAM), dynamic random-access memory (DRAM), and non-volatile memory (e.g., NAND Flash). The trend in the semiconductor industry is toward smaller memory devices that may be used to fabricate high density circuits on a single chip. Miniaturization may be achieved by reducing the size of all the features of surface-oriented devices so that the resultant devices occupy a smaller surface area of a wafer.
Conventional memory devices may include at least one transistor cell used to amplify and switch electronic signals. Such transistor cells may be electrically isolated using shallow trench isolation (STI), for example. With STI, trenches in a substrate are filled with dielectric material to form insulating structures between neighboring transistor cells. The STI structures are formed deep enough to electrically isolate the neighboring cells from each other. However, as transistors are formed on a smaller scale, aspect ratios of the trenches for forming the STI structures increase. As used herein, the term “aspect ratio” means and includes a ratio between a height and a width of a feature, such as a trench in a substrate. As aspect ratios of the trenches are increased, physical stability of the trenches decreases and toppling or other distortion of the substrate in which the trenches are formed becomes a problem. Higher aspect ratios also degrade electrical properties of resulting memory devices due to increased parasitic electrical coupling between neighboring units of a device.
Silicon-on-insulator (SOI) substrates have been used to improve electrical properties of semiconductor memory devices as feature sizes continue to decrease. As used herein, the terms “silicon-on-insulator substrate” or “SOI” mean and include substrates including a silicon material formed over an insulating material (e.g., silicon dioxide or sapphire) overlying another silicon material (also known as bulk silicon). The insulating material provides electrical isolation of the memory cells to be built on or in the top silicon layer from the underlying bulk silicon. This isolation tends to provide lower parasitic capacitance, thus improving power consumption at matched memory performance. Additionally, forming memory cells on an SOI substrate may reduce problems with short circuits that sometimes occur in memory devices, such as those that occur with low-impedance paths inadvertently formed between power supply rails of a metal-oxide-semiconductor field-effect-transistor (MOSFET) and the underlying bulk substrate. This type of short circuit is often referred to as “latchup.” Use of an SOI substrate can reduce latchup problems because the bulk substrate is electrically isolated from the power supply rails of the transistors due to the intermediate insulating layer.
Transistors of semiconductor devices, such as MOSFET devices, including their source, channel, drain, gate and ohmic contacts, may be formed in isolated regions of silicon. During operation, such isolated regions of silicon have a tendency to acquire a potential that may interfere with proper function of the transistor. The problem is often referred to as the “floating body” effect. The floating body effect causes high leakage current and parasitic bipolar action in the semiconductor device, resulting in adverse affects on threshold voltage control and circuit operation.
Although SOI substrates improve electrical properties of devices formed thereon compared to conventional semiconductor substrates, their cost is relatively high. In addition, features at a periphery of the devices used for reading, writing, or erasing information in the memory array may take up extra space on the device and require extra processing steps when an SOI substrate is used, also adding to the cost of the final product. Manufacturing memory devices on an SOI substrate also does not necessarily reduce the aforementioned problems associated with high aspect ratios. Therefore, methods of isolating memory cells from the underlying bulk silicon substrate other than conventional methods of manufacturing memory devices on SOI substrates are desirable to reduce cost, improve device performance, and reduce the occurrence and severity of physical defects.